1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
Various efforts have been made in order to reduce a power supply voltage so that a very large scale integrated circuit (VLSI) operates at a low power consumption. However, if the power supply voltage is reduced, then the delay time, caused by the decrease in the driving power, becomes disadvantageously longer.
In order to operate a complementary metal-oxide-semiconductor (CMOS) device having a conventional structure at a low power supply voltage, the following measures can be taken.
(1) Reducing a thickness of a gate insulting film. PA1 (2) Reducing an effective channel length (or employing a single drain structure). PA1 (3) Suppressing parasitic effects (gate resistance, junction/mirror capacitance, or the like). PA1 (4) Reducing a threshold voltage.
If a device is operated at a low power supply voltage, then an electric field generated by a gate becomes small, so that a leak current is unlikely to flow. Therefore, as compared with a case where the device is operated at a normal voltage, a thinner gate oxide film can be used ((1)). On the other hand, since a drain voltage is also reduced, the degradation caused by hot carriers and a short-channel effect are improved. Therefore, in place of an LDD structure conventionally used for a sub-half micron device, a single drain structure can be used ((2)). As a result, a driving power is considerably reduced.
However, if the above effects (1) and (2) are enhanced, then a gate-drain overlapping capacitance, i.e., a mirror capacitance, increases, and the capacitance gives enormous influence upon the operation of the circuit (as a result, the delay time and the power consumption are much affected). That is why, it is desirable to develop a device structure where the above effects (1) and (2) are realized and a gate-drain overlapping capacitance is small ((3)), in order to realize a satisfactory low-voltage operation.
A T-shaped gate structure allowing for reducing a parasitic capacitance in a gate-drain overlapping lightly-doped drain (LDD) is suggested by K. Kurimoto et al. (IEEE 19911EDM Technical Digest pp. 541-544).
However, the semiconductor device having the T-shaped gate structure disclosed by Kurimoto et al. is not suitable for realizing a semiconductor device having a fine structure in which a region of sub-half micron or less is formed. In a conventional metal-oxide-semiconductor field-effect transistor (MOSFET) mentioned above, side wall oxide films formed on both sides of the gate electrode function as a mask for implanting ions in forming a source and a drain. Accordingly, the source and the drain are shifted to outer positions. As a result, since the effective channel length increases, the driving power of an Nch MOSFET is reduced.
According to the semiconductor device fabrication method disclosed in the above-identified document, after a lightly-doped drain (LDD) is formed by an ion implantation method, a heat treatment is performed at 850.degree. C. for 60 minutes in a wet oxygen environment, thereby oxidizing the surface of a P (phosphorus)-doped poly-silicon gate electrode so as to form a gate bird's beak. This method has the following two problems.
(1) By performing the heat treatment at 850.degree. C. for several tens of minutes after the implantation to form the LDD, the resulting LDD layer diffuses vertically and horizontally, and the degradation is likely to be caused by a short channel effect.
(2) It is difficult to apply this method to a dual-gate technology.